Accurate design of high-performance synchronous buck DC-DC power converters

Accurate power loss calculations are presented for a synchronous buck DC-DC power converter based on simple physics-based circuit models for the switch and inductor. The converter design is shown to be optimized for different die sizes of the high-side and low-side power switches; this design feature becomes important at increased switching frequencies. It is further shown that conventional power loss formulations are in error as they do not accurately calculate the switching power losses. A new figure-of-merit (FOM) is proposed to assess the performance of emerging high-performance power semiconductor switch technologies, especially for low-voltage point-of-load (POL) DC-DC power converters that utilize scaled silicon power MOSFETs and emerging Gallium Nitride (GaN) power transistors.