• DocumentCode
    601598
  • Title

    A 4.6W/mm2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS

  • Author

    Andersen, Toke Meyer ; Krismer, F. ; Kolar, Johann Walter ; Toifl, Thomas ; Menolfi, Christian ; Kull, Lukas ; Morf, Thomas ; Kossel, Marcel ; Brandli, Matthias ; Buchmann, Peter ; Francese, Pier Andrea

  • Author_Institution
    Power Electron. Syst. Lab., ETH Zurich, Zurich, Switzerland
  • fYear
    2013
  • fDate
    17-21 March 2013
  • Firstpage
    692
  • Lastpage
    699
  • Abstract
    The future trends in microprocessor supply current requirements represent a bottleneck for next generation high-performance microprocessors since the number of supply pins will constitute an increasingly larger fraction of the total number of package pins available. This leaves few pins available for signaling. On-chip power conversion is a means to overcome this limitation by increasing the input voltage - thereby reducing the input current - and performing the final power conversion on the chip itself. This paper details the design and implementation of on-chip switched capacitor converters in deep submicron technologies. High capacitance density deep trench capacitors with a low parasitic bottom plate capacitor ratio available in the technology facilitate high power density and efficiency in on-chip switched capacitor converter implementations. The measured performance of a 2 : 1 voltage conversion ratio on-chip switched capacitor converter implemented in 32nm SOI CMOS technology with 1.8V input voltage results in a power density of 4.6W/mm2 at 86% efficiency when operated at a switching frequency of 100MHz.
  • Keywords
    CMOS integrated circuits; DC-DC power convertors; capacitors; silicon-on-insulator; SOI CMOS technology; deep submicron technologies; efficiency 86 percent; frequency 100 MHz; high capacitance density deep trench capacitors; low parasitic bottom plate capacitor ratio; microprocessor supply current requirements; on-chip switched capacitor dc-dc converter; package pins; power density efficiency; size 32 nm; supply pins; voltage 1.8 V;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Applied Power Electronics Conference and Exposition (APEC), 2013 Twenty-Eighth Annual IEEE
  • Conference_Location
    Long Beach, CA
  • ISSN
    1048-2334
  • Print_ISBN
    978-1-4673-4354-1
  • Electronic_ISBN
    1048-2334
  • Type

    conf

  • DOI
    10.1109/APEC.2013.6520285
  • Filename
    6520285