Paving the way for ultimate device scaling through nanoelectronic device simulations

Through full-band and atomistic simulations based on the nearest-neighbor tight-binding model, we investigate how far n-type Si nanowire field-effect transistors can be scaled depending on their crystal orientation and cross section size. Both a three-dimensional quantum transport solver relying on the Non-equilibrium Green´s Function (NEGF) formalism and an improved one-dimensional “top-of-the-barrier” model including source-to-drain tunneling are employed as analysis tools. It is found that a very high mobility, which is usually highly desired, might become a disadvantage in ultra-short devices where source-to-drain tunneling dominates the OFF-state current. In effect, a low effective mass is required to obtain a high mobility, but it also increases the tunneling probability through the gate-induced potential barrier, therefore deteriorating the subthreshold region of the transistor. Another key result is that electron-phonon scattering still plays an important role down to 5 nm gate length.