Gate-all-around Si nanowire array tunnelling FETs with high on-current of 75 µA/µm @ VDD=1.1V

Gate-all-around Si nanowire array p-type tunneling field effect transistors (GAA NW p-TFETs) have been fabricated on thin SOI. High on-current of 75 μA/μm at V_D=V_G=1.1V (=V_DD) was observed. Asymmetric junctions were formed to suppress ambipolar switching typical for all silicon TFETs. Nickel aluminum silicide NiAl_0.2Si_1.8 was used to create high quality single crystalline metal source/drain contacts with matched lattice parameter to the silicon substrate. Implantation into silicide (IIS) method created the n⁺⁺-junctions after outdiffusion of the dopants with a low temperature thermal anneal at 500°C in forming gas (FG). TCAD simulations confirm TFET operation and qualitatively demonstrate the suppression of ambipolarity by optimization of the drain contact.