An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies

Accurate estimation of delay is a major challenge in current nanometer regime using Non Linear Delay Model (NLDM) due to issues such as parametric variation, nonlinear capacitance value etc. It demands a large number of simulations to be performed for getting the accurate delay values. To partly solve this issue, people have started using Effective Current Source Model (ECSM), which stores certain predefined Threshold Crossing Point (TCP) of the output voltage waveform with respect to different input transition time (T_R) values and load capacitance (C_l). In this work, we propose an analytical timing model relating 10% - 90% TCPs with C_l and T_R values. We also derive the relationship between the cell size and the model coefficients. We also derive the region of validity of the model in (T_R, C_l) space and determine its relationship with cell size. The proposed model is in good agreement with HSPICE simulations with a maximum relative error of 2.5%. We verified the proposed model with technology scaling. We use this model and the relationships to reduce the number of simulations in ECSM library characterization.