Leakage Minimization of 10T Full Adder Using Deep Sub-micron Technique

In this paper we introduced low leakage 10T one-bit full adders cells are proposed for mobile applications. The analysis has been performed on various process and circuits techniques, the analysis with leakage power. We introduced a new transistor resizing approach for 1bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power and area to minimize leakage current. We have performed simulations using Cadence Virtuoso 45nm standard CMOS technology at room temperature with supply voltage of 0.7V. Simulations have been also compared for multiple VDD. Thus design guide-lines have been derived to select the most suitable topology for the design features required. This paper also proposes a novel figure of merit to realistically compare 1-bit adders implemented as a chain of one-bit full adders. The CMOS leakage current at the process level can be decreased by some implement on deep sub micron method. The circuit level technique is reduced power consumption at very high level. In this paper we simulate the 10T Adder using many techniques both circuit level, process level.