• DocumentCode
    603376
  • Title

    An Alternate Strategy of SoC Testing

  • Author

    Ghosh, Prosenjit ; Ghosh, Sudip

  • Author_Institution
    Freescale Semicond. India Pvt Ltd., Noida, India
  • fYear
    2013
  • fDate
    6-8 April 2013
  • Firstpage
    706
  • Lastpage
    710
  • Abstract
    As more and more peripherals are integrated in System-On-Chip (SoC), the production testing cost per device is increasing sharply, which is eating up the gross margin of the product significantly. This paper proposes an alternate scheme for production testing whereby major part of the SoC testing can be done with a pre-tested and pre-verified custom made SoC. It will help to minimize the dependencies of Automatic Test Equipment (ATE) for SoC testing in production significantly. Hence production testing cost per device will be reduced. Also this scheme will enable to test many of the functional features of SoC on silicon, which were not possible to test using ATE due to high test cost. In this paper the micro architectural details of the scheme, system requirements, design challenges and case study conducted on different SoCs are presented. And the impact of this approach is also discussed.
  • Keywords
    automatic test equipment; production testing; system-on-chip; SoC testing; automatic test equipment; production testing cost; system-on-chip; Clocks; Delays; Production; Software; System-on-chip; Testing; ATE; I/O AC timing testing; SoC testing; Testing of I/O interfaces; delay measurement; production testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communication Systems and Network Technologies (CSNT), 2013 International Conference on
  • Conference_Location
    Gwalior
  • Print_ISBN
    978-1-4673-5603-9
  • Type

    conf

  • DOI
    10.1109/CSNT.2013.151
  • Filename
    6524494