Effect of Process Variation on Power and Delay in CMOS Circuits

The scaling in the complementary metal oxide semiconductor (CMOS) causes very huge effects in ultra large scale integration (ULSI). The scaling in the CMOS devices is also the fundamental need for VLSI in past few years. There are two types of scaling generally constant voltage (CV) scaling and constant electric (CE) field scaling. The constant electric field scaling is used for the High reliability and performance characteristics of devices. The high voltage scaling is used to get advanced performance and to maintain transistor-transistor logic compatibilities of CMOS circuits. The power and delay are much more important issues to analyze when we scale down any of the devices under name of technology. The variation in process as a function of gate oxide thickness (tox), channel resistance (Rdsw), effective channel length (Leff ) and threshold voltage(Vth ) of CMOS should also be under consideration.