A Successive Approximation A/D Converter Using Generalized Non-Binary Algorithm

An 8-bit successive approximation analog-to-digital converter (SA ADC) has been designed and fabricated by using a 0.18-μm technology. A generalized non-binary algorithm has been used to enhance operation speed by relaxing the settling constraint of the DAC output. A split-capacitor array with a monotonic switching scheme has also been incorporated to reduce the power consumption. Transistor-level simulation shows an effective number of bits (ENOB) of 7.91 bits under a Nyquist condition with a sampling frequency of 2 MHz. Fabricated chip operates successfully, proving the design principle.