• DocumentCode
    603515
  • Title

    Expandable MVL Inverter Compatible with Standard CMOS Process and Its Application to MVL Hysteresis Comparator

  • Author

    Mannan, A.A. ; Tanno, Keita ; Tamura, H. ; Toyama, T. ; Darmawansyah, A.

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Univ. of Miyazaki, Miyazaki, Japan
  • fYear
    2013
  • fDate
    22-24 May 2013
  • Firstpage
    260
  • Lastpage
    265
  • Abstract
    In this paper, a novel voltage-mode MVL inverter is proposed. The proposed inverter consists of two circuit blocks: MVL threshold comparator and Multi-level generator, which can be implemented by standard CMOS technologies. Next, the inverted MVL hysteresis comparator is also proposed as the application of the proposed MVL inverter. The proposed MVL inverter and inverted MVL hysteresis comparator are expandable, capable to use more numbers of levels in MVL circuits. The performances of all proposed MVL circuits were evaluated through HSPICE with the set of 0.18μm CMOS process parameters. From the simulation results, we could confirm that all proposed MVL circuits work well as theory.
  • Keywords
    CMOS logic circuits; comparators (circuits); logic gates; multivalued logic; HSPICE; MVL circuits; MVL threshold comparator; circuit blocks; expandable MVL inverter; inverted MVL hysteresis comparator; multilevel generator; size 0.18 mum; standard CMOS process; standard CMOS technology; voltage-mode MVL inverter; Detectors; Generators; Hysteresis; Inverters; MOSFET; Simulation; Threshold voltage; hysteresis comparator; inverter; multiple-valued logic; threshold detector;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on
  • Conference_Location
    Toyama
  • ISSN
    0195-623X
  • Print_ISBN
    978-1-4673-6067-8
  • Electronic_ISBN
    0195-623X
  • Type

    conf

  • DOI
    10.1109/ISMVL.2013.27
  • Filename
    6524674