DocumentCode
603740
Title
Managing performance and efficiency of a processor
Author
Shinde, A. ; Agrawal, Vishwani D.
Author_Institution
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
fYear
2013
fDate
11-11 March 2013
Firstpage
59
Lastpage
62
Abstract
The performance of a processor generally means how fast it can execute a task. For a given architecture we can measure the size of a task as the number of clock cycles it will take to execute. Then clock frequency (f) will determine the execution time. Normally, the frequency can be raised if the supply voltage Vdd is increased. This, however, increases the power and energy used. We introduce a new measure, cycle efficiency (η) as cycles per joule that gives the rate of computational work per unit energy. Similar to f, η is also a function of Vdd. We provide a method of characterizing a processor in terms of its f and η versus Vdd characteristics. Intel Pentium M processor with an assumed 90nm CMOS PTM (predictive technology model) is used as an example. For a demonstration of performance and energy management, we consider a program that executes in 1.8 billion clock cycles. At the nominal operating supply of 1.2V we have f = 1.8GHz and η = 15 megacycles/joule. The program executes in 1 second and uses 120 joules. For operation at 0.6V, f = 277MHz and η = 70 megacycles/joule, resulting in a run time of 6.5 seconds and consumption of 25 joules. We also find a subthreshold voltage extreme of 200mV, f = 54.5MHz and η = 660 megacycles/joule. Now the program will take 33 seconds but will consume only 2.27 joules. Thus, using cycle efficiency and clock frequency one can manage the time and energy performances according to the requirements of a computing task.
Keywords
microprocessor chips; performance evaluation; CMOS PTM; Intel Pentium M processor; clock frequency; complimentary metal oxide semiconductor; computational work; cycle efficiency; execution time; predictive technology model; processor efficiency; processor performance management; supply voltage; unit energy; CMOS integrated circuits; Clocks; Delays; Educational institutions; Integrated circuit modeling; Semiconductor device modeling; Time-frequency analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
System Theory (SSST), 2013 45th Southeastern Symposium on
Conference_Location
Waco, TX
ISSN
0094-2898
Print_ISBN
978-1-4799-0037-4
Type
conf
DOI
10.1109/SSST.2013.6524953
Filename
6524953
Link To Document