Semi empirical cadmium sulfide transistor model combining grain defects and semiconductor thickness variation

Proposed and tested is a methodology for modeling polycrystalline thin film transistors which exhibit shifts in threshold voltage due to both grain boundaries and semiconductor thickness. The process involves a model, which uses in part standard-analytic terms. It also includes terms for grain defects and for thickness added in using numerical simulation testing. From this testing, the threshold voltage for the CdS transistor exhibited an optimum thickness for enhancement mode operation. The semi empirical model was then brought into alignment with experimental results for a CdS transistor by adjusting the interface charge. Predictions from the semi empirical model produced transistor output characteristic and transfer curves showed to be in good agreement with experimental data.