Achieving non-polluting cache accessing by using data valid tag splitting

Rapid progress of Semiconductor fabrication provides capacious space for IC designs, but unfortunately, the slow development of design ability makes it difficult to utilize the on-chip resource efficiently. At present, more than half of die area of modern microprocessor is inhabited by cache. So, how to make use of cache space smartly and efficiently, and construct high performance memory system has become one of the most important content in processor architecture design. This paper analyses of the impacts of cache data pollution and speculative execution to processor performance, and proposes a non-polluting cache accessing technique based on data tag valid-bit splitting, which is called Pease. Firstly, we splits the valid-bit in D-Cache tag into two bits, reading data valid bit (RVB) and writing data valid bit (WVB). Secondly, according the different RVB and WVB combinations, corresponding accessing strategies to D-Cache are applied. As a result, Pease technique not only preserves the pre-fetch ability of speculative execution, but also makes the cache polluting data transparent, which means that, in no empty cache line situation, consequent data can be written into D-Cache directly, but without need to perform cache replacement operation. In other word, Pease technique makes polluting data totally harmless to D-cache. Simulation result indicates that, relative to the baseline architecture, Pease technique improves IPC from 1.05% to 8.40%, averagely 4.04%, and reduces miss rate of D-Cache from 19.05% to 48.16% averagely 29.66%.