A Low Power 10-Bit Time-to-Digital Converter Utilizing Vernier Delay Lines

Author

Wei Chen ; Papavassiliou, Christos

Author_Institution

Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK

fYear

2013

fDate

10-12 April 2013

Firstpage

774

Lastpage

779

Abstract

A low power CMOS time-to-digital converter with resolution adjustable is presented in this paper. The proposed converter is consisted of a counter and two vernier delay lines to achieve the asynchronous measurement. The internal reference clock is formed by a single-end ring oscillator. The delay lines both in reference clock and the vernier delay lines are controlled by a current source, which makes the system to realize resolution adjustable between 8.5ns and 51ns. The whole system is operated by a dual 0.6V supply with 10-bit binary output. The simulated power consumption is less than 10uW. The differential nonlinearity (DNL) error of the vernier delay line is within 0.04LSB, and the integral nonlinearity (INL) error is within 0.05LSB.

Keywords

CMOS integrated circuits; analogue-digital conversion; clocks; delay lines; low-power electronics; oscillators; asynchronous measurement; differential nonlinearity error; integral nonlinearity error; internal reference clock; low power CMOS time-to-digital converter; power consumption; single-end ring oscillator; vernier delay lines; voltage 0.6 V; word length 10 bit; Clocks; Current measurement; Delay lines; Delays; Interpolation; Radiation detectors; Time-to-digital converter; current controlled delay line; vernier delay line;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Modelling and Simulation (UKSim), 2013 UKSim 15th International Conference on

Conference_Location

Cambridge

Print_ISBN

978-1-4673-6421-8

Type

conf

DOI

10.1109/UKSim.2013.86

Filename

6527517