FPGA implementation of genetic algorithm for dynamic filter-bank-based multicarrier systems

This paper presents FPGA implementation of a genetic algorithm based canonical signed digit (CSD) synthesizer for a dynamic filter-bank-based multicarrier system which employs a regular prototype filter with a certain specification. Using Genetic Algorithm, the proposed system searches for the best coefficients of prototype filter in CSD format for the filter bank based multicarrier (FBMC) system. The system is reconfigurable so that filter characteristics (number of coefficients) and their precisions (number of bits) for each coefficient can be set dynamically. Finally, the design is entirely implemented on a field programmable gate array (FPGA) chip. Simulations and synthesis results are obtained to show the merit of the proposed design. Results demonstrate that the system needs less than one second to provide desired filter coefficients when a prototype filter with 64 coefficients is employed.