A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM

The fast growth of battery operated devices has made low power SRAM designs a necessity in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The SRAM performance is limited by the cell stability during different operation. By adding extra transistor to the conventional 6T-cell, hold, read and write static noise margin (SNM) can be improved in the sub-threshold SRAM. In this paper we proposed a new 9T-cell SRAM that shows 80% and 50% improvement in read and write SNM respectively in comparison to the conventional 6T-cell SRAM. Using stack transistors in the leakage current path, the new structure shows lower bitline leakage assisting the sense amplifier to easily read the bitline current. The 0.3V sub-threshold SRAM post-layout simulation using 90nm TSMC CMOS model confirms the proposed 32k SRAM performance.