Energy efficient and hign bandwidth embedded memory implementation

Embedded memory is an important part of processors and system on Chip main matrix (performance, power and area). As a result, the ever increasing integration of embedded memory continues. SRAM cell is the preferred option for embedded memory because of low power density, smaller area, layout regularity, and high performance. Implementation options and organization of such memory have big impact on the power, area, and performance. The goal of this paper is to analyze the different options available for SRAM to enable energy efficient implementation including low voltage operation. The paper will present the findings of implementing high bandwidth (256-bit) L1 cache using SRAM cell with full swing bitline using 28nm foundry process technology. The result shows the design with full swing is more power efficient (10% less array power) than small swing sense amplifier based scheme. The area for the two design are compatible with 4-5% more area overhead for full swing. The proposed design support wordline overdrive assist circuit during write access to enable low voltage operation.