Implementation of programmable logic array using SET-CMOS hybrid approach

The layout of programmable logic array allows for a large number of logic functions to be synthesized in the sum of product canonical form. This paper presents the design and implementation of programmable logic array (PLA) with SET-CMOS hybrid technology. The PLA is represented as a three layered architecture where each of the layer is implemented applying the hybrid approach. As here, we are using two different technologies namely single electron tunneling technology and CMOS technology, so the logical operation of the designed PLA is governed by the combination of two complementary technologies. We have verified the proper functionality of the designed circuit by simulating it using Tanner spice simulator.