• DocumentCode
    606158
  • Title

    Efficient VLSI architecture of medium throughput AES encryption

  • Author

    Panigrahi, Swetalina ; Sharma, V.K. ; Das, Chinmayee ; Mahapatra, Kamala Kanta

  • Author_Institution
    Department of Electronics and Communication Engineering, National Institute of Technology Rourkela, India-76900
  • fYear
    2013
  • fDate
    20-21 March 2013
  • Firstpage
    975
  • Lastpage
    978
  • Abstract
    This paper presents an efficient VLSI architecture design of Advanced Encryption Standard (AES) algorithm for medium throughput applications. The architecture stores the Round Key in ROM instead of registers. The proposed AES architecture for encryption has been implemented in XC2VP30 device on Xilinx Virtex-II FPGA board. With low hardware utilization, it achieves a medium throughput of 1.2 Gbps and also it has low power dissipation.
  • Keywords
    Encryption; Iron; Read only memory; Table lookup; Throughput; AES Encryption; FPGA Implementation; Low Cost Architecture;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits, Power and Computing Technologies (ICCPCT), 2013 International Conference on
  • Conference_Location
    Nagercoil
  • Print_ISBN
    978-1-4673-4921-5
  • Type

    conf

  • DOI
    10.1109/ICCPCT.2013.6528914
  • Filename
    6528914
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=606158