Performance analysis of a new CMOS output buffer

A new CMOS output buffer with low switching noise and load adaptability is presented in this paper. The proposed circuit consists of two stages; first stage is set to reduce switching noise, static power dissipation and also output ringing. The second stage involves enough speed and full dynamic range. The performance of the proposed circuit is examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results have confirmed that the proposed output buffer can reduce propagation delay compared with the previous designs. The topology reports low sensitivities and has features suitable for VLSI implementation.