FPGA implementation of pipelined CORDIC based quadrature direct digital synthesizer with improved SFDR

Direct Digital Synthesizers (DDSs) or Numerically Controlled Oscillators (NCOs) are nowadays prominently used in the applications of RF signal processing, satellite communications, etc. This paper brings out the FPGA implementation of one such DDS which has quadrature outputs. The proposed design, which is based on pipelined CORDIC, has considerable improvement in terms of spurious free dynamic range (SFDR) compared to other existing designs at reduced hardware. The design is implemented on Xilinx XC3S500E-4FG320 FPGA, fabricated in 90 nm process technology. The design has utilized 487 slices and 967 4-input look up tables (LUTs) as its hardware count. The maximum sampling frequency of the proposed design is 107.216 MHz. The SFDR of proposed DDS is −96.31 dBc.