Double-Run-length compression of test vectors scheme for variable-length to variable-length

As the current testing system on a chip requires a lot of test vectors, which will increase the test time and cost. Methods of increased the testability of the design and compression of test vectors are widely used to solve this problem. This paper presents a new Double-Run-length compression of test vectors scheme which is from the variable length to variable-length, and achieves the relevant hardware circuit. Double-Run-length encoding, not only avoid the negative phenomenon of test data compression, but do not have to consider the nature of the test data as well. That is, whether the data appear more 0 or 1 situation, testing system will get a better compression ratio.