On the FPGA implementation of empirical mode decomposition algorithm using FPGA

In this paper a single chip hardware architecture for empirical mode decomposition is proposed and implemented on a consumer grade FPGA device. Implementing EMD on a single chip dramatically decreases hardware costs and increases real time processing performance. Proposed hardware architecture has utilized %17 of the LUT resources of a consumer grade FPGA. Even though the proposed architecture operates on single dimensional signals such as EEG, sound etc., it can also be considered for decomposing multidimensional signals such as image, video, hyper spectral images.