An age-aware library for reliability simulation of digital ICs

Author

Katoozi, M. ; Cannon, E.H. ; Tuan Dao ; Aitken, K. ; Fischer, Shannon ; Amort, T. ; Brees, R. ; Tostenrude, J.

Author_Institution

Boeing Co., Seattle, WA, USA

fYear

2013

fDate

14-18 April 2013

Abstract

A general method for creating an age-aware library of cells, including the impact of multiple reliability degradation mechanisms, is presented. The underlying degradation models take into account key reliability-impacting parameters such as input slew rate, output load, signal toggle rate, signal activity factor, output buffer size and age. A framework for using this age-aware library to analyze the aging of digital Integrated Circuit (IC) timing performance using existing Electronic Design Automation (EDA) methodologies is also discussed.

Keywords

circuit simulation; digital integrated circuits; electronic design automation; integrated circuit design; integrated circuit reliability; EDA; age-aware library; digital IC; digital integrated circuit; electronic design automation methodology; input slew rate parameter; multiple reliability degradation mechanism; output buffer size parameter; output load parameter; reliability simulation; reliability-impacting parameter; signal activity factor parameter; signal toggle rate parameter; timing performance; Aging; Analytical models; Data models; Load modeling; Logic gates; Reliability; Timing; HCI; NBTI; TDDB; age-aware; cell library; degradation models; reliability; static timing analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4799-0112-8

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2013.6531973

Filename

6531973