Duty-cycle shift under asymmetric BTI aging: A simple characterization method and its application to SRAM timing

Author

Xiaofei Wang ; Keane, John ; Jain, Paril ; Reddy, Veerababu ; Kim, Chul Han

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA

fYear

2013

fDate

14-18 April 2013

Abstract

The effect of DC BTI stress on the clock signal´s duty-cycle has been experimentally verified for the first time based on the precise frequency shift measurement from Ring OSCillators (ROSC). A simple and practical methodology based on the “silicon odometer” beat-frequency detection framework has been proposed for accurately measuring duty-cycle shifts while preventing unwanted BTI recovery. The measurement results from a 65nm test chip were used to further analyze the impact of asymmetric BTI aging during clock gated mode on SRAM timing signals.

Keywords

SRAM chips; ageing; distance measurement; elemental semiconductors; frequency measurement; integrated circuit measurement; integrated circuit testing; oscillators; silicon; stress analysis; timing circuits; DC BTI stress effect; ROSC; SRAM timing signal; Si; asymmetric BTI aging; bias temperature instability; clock gated mode; clock signal duty-cycle shift measurement; precise frequency shift measurement; ring oscillator; silicon odometer beat-frequency detection framework; size 65 nm; unwanted BTI recovery; Aging; Clocks; Degradation; Delays; Logic gates; Random access memory; Stress; Duty-cycle; SRAM; asymmetric aging; bias temperature instability; degradation;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4799-0112-8

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2013.6532007

Filename

6532007