ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process

Author

Chang-Tzu Wang ; Yu-Chun Chen ; Tien-Hao Tang ; Kuan-Cheng Su

Author_Institution

ESD Eng. Dept., United Microelectron. Corp., Hsinchu, Taiwan

fYear

2013

fDate

14-18 April 2013

Abstract

An N-channel electrostatic discharge (ESD) protection device with DNW sinker has been designed without latch-up risk for 5-V operating condition. With the DNW sinker, the NMOS snapback behavior can be restrained and the holding voltage can be increased. The proposed ESD protection device can sustain 3.6kV human-body-model (HBM) and 325V machine model (MM) ESD tests. With holding voltage of 6.4V, the latch-up test shows the immunity from 7.5V voltage test and 200-mA current test.

Keywords

CMOS integrated circuits; electrostatic discharge; CMOS process; DNW sinker; ESD protection design; HBM; MM; N-channel electrostatic discharge protection device; NMOS snapback behavior; adjustable snapback behavior; current 200 mA; holding voltage; human-body-model; machine model; size 100 nm; voltage 3.6 kV; voltage 325 V; voltage 5 V; voltage 6.4 V; voltage 7.5 V; Breakdown voltage; Current density; Current distribution; Electrostatic discharges; Implants; Layout; MOSFET circuits; electrostatic discharge (ESD); hodling voltage; latch-up;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4799-0112-8

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2013.6532072

Filename

6532072