A low leakage poly-gated SCR device for ESD protection in 65nm CMOS process

Author

Parthasarathy, Srinivasan ; Salcedo, Javier A. ; Hajjar, Jean-Jacques

Author_Institution

Analog Devices. Inc., Wilmington, MA, USA

fYear

2013

fDate

14-18 April 2013

Abstract

A low-leakage, low triggering polysilicon bounded SCR design is introduced for on-chip electrostatic discharge (ESD) protection in CMOS applications. The advantages of replacing the shallow trench isolation (STI) with a polysilicon gate in the device formation are discussed. The device response to fast transients, emulating ESD CDM-type events, is discussed through VFTLP measurements. The low-leakage characteristics of the SCR clamp are also demonstrated via high temperature measurements.

Keywords

CMOS integrated circuits; electrostatic discharge; leakage currents; thyristors; CDM-type events; CMOS process; ESD protection; STI; VFTLP measurements; clamp; device formation; high temperature measurements; low leakage poly-gated SCR device; low triggering polysilicon bounded SCR design; on-chip electrostatic discharge protection; shallow trench isolation; silicon controlled rectifiers; size 65 nm; Capacitance; Current measurement; Electrostatic discharges; Logic gates; Radio frequency; Thyristors; Charged Device Model (CDM); Electrostatic Discharge (ESD); Leakage Current; Radio Frequency (RF); Silicon Controled Rectifier (SCR);

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4799-0112-8

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2013.6532074

Filename

6532074