Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application

Author

Rahman, Aminur ; Bai, P. ; Curello, G. ; Hicks, J. ; Jan, C.-H. ; Jamil, M. ; Park, Jongho ; Phoa, K. ; Rahman, Md Saifur ; Tsai, Chia-Yin ; Woolery, B. ; Yeh, J.-Y.

Author_Institution

Logic Technol. Dev. Quality & Reliability, Intel Corp., Hillsboro, OR, USA

fYear

2013

fDate

14-18 April 2013

Abstract

Transistor reliability characterization studies are reported for a state of the art 22nm 3-D tri-gate HK/MG SoC technology with logic and HV I/O transistor architecture. TDDB, BTI and HCI degradation modes for logic and I/O transistors are studied and excellent reliability is demonstrated. In order to simultaneously integrate logic and HV 3-D tri-gate transistors with robust reliability, the importance of process optimization is emphasized.

Keywords

CMOS integrated circuits; integrated circuit reliability; negative bias temperature instability; system-on-chip; three-dimensional integrated circuits; 3D trigate integrated circuit; BTI; HCI degradation mode; SoC platform technology; TDDB; high density application integrated circuit; process optimization; reliability study; size 22 nm; transistor reliability; ultra low power integrated circuit; Degradation; Dielectrics; Logic gates; MOS devices; Reliability; System-on-chip; Transistors; BTI; CMOS; High-K dielectric; Reliability; SILC; SoC; TDDB; breakdown; metal gate; tri-gate;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4799-0112-8

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2013.6532105

Filename

6532105