A load-balanced pipeline architecture for IP route lookup

We present in this article a pipeline architecture built with multiple memory blocks for IP route lookup using trie-based routing algorithms. A two-hierarchy prefix distribution scheme is employed to balance the storage demands among the memory blocks, where prefixes not longer than r bits in the routing table are mapped to an index table and the remaining prefixes are organized into multiple prefix tries according to their highest r bits. An access control strategy is employed to avoid access conflicts in the routing system when multiple packets attempt to access a same memory block. For this purpose, a load balancer consisting of two groups of buffers connected by a rotator, is employed to distribute to memory blocks the searching requests of IP lookups for arriving packets. The simulation results indicate that the proposed multi-block pipeline routing architecture can achieve nearly 100% throughput under typical IPv4 corpora with uniform distributed destinations.