Future concepts for on-board timing subsystems for navigation satellites

All signal generation and transmission frequencies in the payload of a navigation satellite are typically derived from a single 10.23 MHz master clock. In case of the current payload architecture of the Galileo or other Navigation System this Master Timing Reference (MTR) is synthesized in a Clock Monitoring and Control Unit (CMCU) based on one single atomic reference. To achieve this, in the current Galileo design the CMCU selects the active clock from a pool of two Rubidium Atomic Frequency Standards (RAFS) and two Passive H-Masers (PHM) and synthesizes the MTR from this source. A second atomic clock is kept in hot redundancy and monitored inside the CMCU for its phase drift against the active clock. However this concept does not provide any protection against misbehaviour of the sole active clock in case of unexpected high frequency drifts or frequency jumps. For this reason future concepts are under investigation at Astrium to derive the MTR simultaneously from multiple atomic clocks by composite clock methods supported by frequency jump detection algorithms. This paper describes the hardware concepts for current CMCUs as well as a next generation CMCU based on composite clock techniques including the multi-channel phase comparison system to provide the input source for the algorithms and the frequency synthesis to generate the MTR output frequency.