Timing-aware clock gating of pulsed-latch circuits for low power design

Low power design is a crucial issue in modern circuit design. Several techniques have been developed to save power consumption. Of those techniques, the pulsed-latch technologies replace flip-flops with pulsed latches due to smaller capacitance of the latter. Additionally, the clock gating of pulsed-latch circuit, which is called pulser gating, has been developed recently to further reduce power consumption. However, pulser gating may incur a timing violation in the clock gating cell, making it impossible to operate the pulser gating correctly, and ultimately causing a fatal error in the circuits. Therefore, this work propose an algorithm to resolve the problem of pulser gating and timing constraints simultaneously. We use a line-search algorithm to determine gate location to satisfy the timing constraint and apply the minimum-cost maximum-flow network to globally determine the clock-tree topology of pulsed-latch circuits. Experimental results indicate that the proposed algorithm can reduce power consumption with timing constraint effectively compared to state-of-the-art proposed.