A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizer

Author

Chen-Chien Lin ; Chan-Hsiang Weng ; Tsung-Hsien Lin

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2013

fDate

22-24 April 2013

Firstpage

1

Lastpage

4

Abstract

A dual-mode (2^nd/3^rd-order) continuous-time delta-sigma modulator with a proposed 4-bit folded quantizer is presented. The proposed folded quantizer achieves lower power consumption and saves quantizer hardware area. In addition, the dual-mode architecture provides the flexibility to satisfy the power consumption and resolution requirement. With a 1-MHz bandwidth and 64-MHz sampling rate, the measured peak SNDR and dynamic range for 2^nd/3^rd-order modulators are 55 dB/66 dB and 57 dB/68 dB, respectively. Fabricated in a 90-nm CMOS, the chip consumes 1.2 mW/1.5 mW from a 1.2-V supply voltage.

Keywords

CMOS integrated circuits; delta-sigma modulation; integrated circuit manufacture; low-power electronics; power consumption; CMOS; bandwidth 1 MHz; dual-mode architecture; frequency 64 MHz; low-power dual-mode continuous-time delta-sigma modulator; power 1.2 mW; power 1.5 mW; power consumption; quantizer hardware area; size 90 nm; voltage 1.2 V; word length 4 bit; Bandwidth; Modulation; Power demand; Quantization (signal); Signal to noise ratio; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4673-4435-7

Type

conf

DOI

10.1109/VLDI-DAT.2013.6533839

Filename

6533839