Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designs

Aging and soft errors have become the two most critical reliability issues for nano-scaled CMOS designs. In this paper, the aging effect due to negative bias temperature instability (NBTI) is first analyzed on cells using a 45nm CMOS technology for soft errors. Second, an accurate statistical soft-error-rate (SSER) framework is built and incorporates the aging-aware cell models. As a result, two findings are discovered: (1) PMOS-induced transient faults, comparing to NMOS-induced ones, have more variation in pulse widths since PMOS is more susceptible to NBTI; (2) NBTI together with process variation, induces more soft errors (~19%) and thus needs to be considered, simultaneously, during circuit analysis. Experimental result shows that our SSER framework considering both process variation and aging is efficient (with multiple-order speedups) and achieves high accuracy (with <;3% errors) when compared with Monte-Carlo SPICE simulation.