Title :
Low-cost testing of TSVs in 3D stacks with pre-bond testable dies
Author :
Sying-Jyan Wang ; Yu-Siao Chen ; Li, Katherine Shi-Min
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan
Abstract :
A test scheme for through-silicon-vias (TSVs) in three-dimensional integrated circuits (3D-ICs) is proposed. The proposed scheme is applicable as long as each die in a 3D-IC is pre-bond testable; as a result, combining this scheme with low-cost DFT features for pre-bond die test leads to a test flow with low overall test cost. A test pattern generation (TPG) method under the proposed test scheme is developed. Most of the patterns are reused from pre-bond test, which simplifies the TPG flow and reduces overall pattern counts as well. Experimental results show that the proposed method can detect TSV faults efficiently with very low hardware overhead.
Keywords :
design for testability; fault diagnosis; integrated circuit bonding; integrated circuit testing; microassembling; three-dimensional integrated circuits; 3D-IC stack; TPG; TSV fault detection; flow test; low-cost DFT feature; pre-bond die testing; test pattern generation method; three-dimensional integrated circuit; through-silicon-vias; Automatic test pattern generation; Circuit faults; Discrete Fourier transforms; Hardware; Three-dimensional displays; Through-silicon vias;
Conference_Titel :
VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4673-4435-7
DOI :
10.1109/VLDI-DAT.2013.6533888
