Efficient test and repair architectures for 3D TSV-based random access memories

In this paper, we propose a test and repair architecture for 3D ICs consisting of stacked memory dies (slave dies) and a processor die (master die). The proposed architecture supports known-good-die (KGD) test, known-good-stack (KGS) test, and final test and repair. However, instead of incorporating spare elements in each memory die, a small-size redundant memory is incorporated into the processor die. That is, the added redundancy can be used globally for repairing faulty cells among all other stacked memory dies. Each slave die contains the BIST and BIRA modules for performing KGD and KGS tests and redundancy analysis. The results of redundancy analysis then can be used for die stacking, yield management, and BISR (built-in self-repair) after the final test. An 1149.1-based test interface is added for each slave die and only four test pads are required for test and repair purposes. Based on the results of the BIRA module, a simple matching algorithm is proposed to increase the stacking yield. According to experimental results, the hardware overhead for an 8K × 32-bit SRAM is only 2.6%. Moreover, the stacking yield can be improved significantly.