New probabilistic reliability model describing the risk of chip fracture in the chip-on-board technology

Due to increased demands for the integration density of electronics, a turnaround in packaging technology has taken place, away from packaged constructions towards chip-onboard technology. A particular challenge of this technology is the avoidance of chip fracture during processing and subsequent use. In the present study a method was worked out which combines the two relevant factors for chip fracture. On the one hand it is the stress during packaging and subsequent use while on the other hand it is the stress resistance of the chips. For this reason various dicing technologies were studied and the corresponding fracture strength of the chips was analysed. Damages induced by the dicing were studied using scanning electron microscopy. Also the chip size effect was investigated. All obtained results were used to develop a probabilistic reliability model for the chip-on-board technology which describes the risk of chip fracture during the die attachment.