A novel X-ray diffraction technique for analysis of die stress inside fully encapsulated packaged chips

Manufacturing-induced thermal stress created during the fabrication of packaged integrated circuits can potentially lead to device failure. Therefore, the need to develop metrologies that can be used to effectively measure stress/strain in systems-on-chip or systems-in-package is identified by the International Technology Roadmap for Semiconductors (ITRS). In this study, a novel technique for non-destructive analysis of strain/warpage inside completely encapsulated packaged chips, at room temperature and processed at elevated temperatures up to 115°C, is developed using a laboratory-based X-ray diffraction tool. Maps are produced of the entire silicon die, which reveal warpage via mapping of rocking curve full-widths-at-half-maximum (FWHM) as a function of position across encapsulated packages, using a technique known as 3-dimensional surface modelling. We develop complete Si die maps of the large thermal stresses that are developed during the die attach process due to the coefficient of thermal expansion mismatch between different materials. These are confirmed by in situ X-ray diffraction annealing experiments, as well as finite element analysis (FEA).