DocumentCode
609795
Title
Self-aligned through silicon vias in ultra-thin chips for 3D-integration
Author
Ferwana, Saleh ; Harendt, Christine ; Letzkus, Florian ; Burghartz, Joachim N.
Author_Institution
Institute for Microelectronics Stuttgart (IMS CHIPS), Allmandring 30a, 70569 Stuttgart, Germany
fYear
2012
fDate
17-20 Sept. 2012
Firstpage
1
Lastpage
4
Abstract
Here, we present a new concept for enabling the formation of TSVs in ultra-thin chips fabricated by using the ChipfilmTM technology. In this technology a buried cavity is created underneath a Si-membrane which is attached to the substrate by vertical silicon anchors. By applying thermal oxidation, the side walls of these anchors and the narrow cavity are passivated. Due to the high selectivity of the silicon via etching process the oxidized silicon anchors and chip backside can be exploited for creating self-aligned TSVs. Accordingly, a seamless oxide isolation at the chip backside and inside the TSVs is provided.
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic System-Integration Technology Conference (ESTC), 2012 4th
Conference_Location
Amsterdam, Netherlands
Print_ISBN
978-1-4673-4645-0
Type
conf
DOI
10.1109/ESTC.2012.6542114
Filename
6542114
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