Systematic design of 10-bit 50MS/s pipelined ADC

Author

Kehan Zhu ; Balagopal, S. ; Saxena, Vishal

Author_Institution

Dept. of Electr. & Comput. Eng., Boise State Univ., Boise, ID, USA

fYear

2013

fDate

12-12 April 2013

Firstpage

17

Lastpage

20

Abstract

A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-V_pp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; operational amplifiers; pipeline processing; power consumption; CMOS process; ENOB; SFDR; SNR; effective number of bits; frequency 4.858 MHz; opamp-sharing technique; pipelined ADC; power 24 mW; power consumption; signal-to-noise ratio; sinusoid input; size 130 nm; spurious free dynamic range; systematic design; systematical design analysis; voltage 1.2 V; Capacitors; Clocks; Equations; Latches; Noise; Switches; Topology; ENOB; Pipelined ADC; SFDR; SNR;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electron Devices (WMED), 2013 IEEE Workshop on

Conference_Location

Boise, ID

ISSN

1947-3834

Print_ISBN

978-1-4673-6034-0

Type

conf

DOI

10.1109/WMED.2013.6544508

Filename

6544508