Title :
Demonstration of chip level writability, endurance and data retention of an entire 8Mb STT-MRAM array
Author :
Lee, Y.J. ; Jan, G. ; Wang, Y.J. ; Pi, K. ; Zhong, Tao ; Tong, R.Y. ; Lam, V. ; Teng, Jun ; Huang, Kejie ; He, R.R. ; Le, S. ; Torng, T. ; DeBrosse, J. ; Maffitt, T. ; Long, C. ; Gallagher, W.J. ; Wang, P.K.
Author_Institution :
TDK-Headway Technol. Inc., Milpitas, CA, USA
Abstract :
We demonstrate the writability of an entire 8 Mb STT-MRAM chip and present data on the expected endurance and data retention up to 90°C. The chip utilizes a device structure that displays high spin-transfer torque efficiency and proper write-current scaling, down to write pulse width of about 1.5 ns.
Keywords :
MRAM devices; STT-MRAM array; STT-MRAM chip; chip level writability; data retention; device structure; spin-transfer torque efficiency; write pulse width; write-current scalin; Arrays; Energy barrier; Magnetic field measurement; Performance evaluation; Switches; Temperature measurement; Writing;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4673-3081-7
Electronic_ISBN :
978-1-4673-6422-5
DOI :
10.1109/VLSI-TSA.2013.6545595
