CMOS reliability: From discrete device degradation to circuit aging

As we continue scaling towards 14 nm and beyond, reliability is becoming an integral part of the complete technology offering. Building in reliability is critical to the success of future scaling. As we marched towards the sub 100 nm technologies material changes have been necessary to meet the power, performance and reliability requirements. In sub 45 nm regime SiOx based dielectrics have been replaced by HK MG leading to new degradation mechanisms such as PBTI and also changed the understanding of existing mechanisms such as TDDB. As we scale further we need to comprehend interaction between device level variability pre and post stress and circuit functionality. In this talk I will address some of the challenges and correlation of device level reliability learning to simple circuits such ring oscillator and SRAM cells.