Effect of fin height of tapered FinFETs on the sub-22-nm System on Chip (SoC) application using TCAD simulation

This work investigates the effect of H_fin on the device and circuit characteristics, and discusses the design aspects for the SoC integration such as 6T-SRAM and 2-stage OPAMPs. Table summarizes the device- and circuit-level assessment using the FinFETs and the planar FETs. Even though the gate control of FinFETs is better than of the planar FETs, further attention should be paid to design H_fin of the FinFETs. SoC blocks such as SRAMs require both high density and low power, so the minimum L_gate will restrict designing H_fin. On the other hand, the analog/RF applications prefer long L_gate to achieve high output resistance for better performance, so we may raise the H_fin without losing the gate control capability. Multiple H_fin design may be good choice for the sub-22-nm SoC integration because H_fin may affect the power, density, and the design convenience.