A Bit of Analysis on Self-Timed Single-Bit On-Chip Links

Author

Tse, Jonathan ; Hill, B. ; Manohar, Rajit

Author_Institution

Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA

fYear

2013

fDate

19-22 May 2013

Firstpage

124

Lastpage

133

Abstract

We present a study of five different self-timed single-bit on-chip links implemented in 90 nm, 65 nm, and 45 nm process technologies. These include representative examples of Quasi Delay-Insensitive, single-track, ternary, and voltage-scaled links, as well as a link of our own design intended to minimize wire usage. We characterize the tradeoffs between throughput, energy, and area for planar wiring as well as 3D through-silicon vias. We also describe our multi-objective optimization framework for exploring this parameter space.

Keywords

asynchronous circuits; circuit optimisation; integrated circuit design; three-dimensional integrated circuits; wiring; 3D through-silicon vias; asynchronous circuit; bit of analysis; multiobjective optimization framework; planar wiring; quasidelay-insensitive links; self-timed single-bit on-chip links; single-track links; size 45 nm; size 65 nm; size 90 nm; ternary-scaled links; voltage-scaled links; 3D integration; ATLS; QDI; STFB; TSV; WCHB; asynchronous; on-chip links; relaxed QDI; single-track; ternary;

fLanguage

English

Publisher

ieee

Conference_Titel

Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on

Conference_Location

Santa Monica, CA

ISSN

1522-8681

Print_ISBN

978-1-4673-5956-6

Type

conf

DOI

10.1109/ASYNC.2013.26

Filename

6546186