Design and implementation of high performance array multipliers for digital circuits

In this paper, two low power and high speed array multipliers have been proposed. The proposed multiplier-1 provides approximately 24% reduction in power consumption and 56% reduction in delay as compared with those of conventional array multiplier. The proposed multiplier-2 is based on new hybrid adder which provides approximately 17% reduction in power consumption and 5% reduction in delay. All designs proposed in this paper have been implemented using UMC 0.18μm CMOS technology. The implementation results show that all new designs have superior performance (reduction in the propagation delay and power consumption) compared to previously proposed designs.