Architecture level TSV count minimization methodology for 3D tree-based FPGA

The CMOS technology scaling has greatly improved the overall performance and density of Field Programmable Gate Array (FPGA), nonetheless the performance gap between FPGA and ASIC has remain very wide mainly due the programming overhead of FPGA. Three-Dimensional (3D) integration is a promising technology to reduce wire lengths. Through Silicon Vias (TSV) provide electrical connectivity between multiple active device planes in 3D integrated Circuits (ICs). TSVs require a significant silicon area compared to planar interconnects and also bring critical challenges to design of 3D ICs. In this paper we propose an architectural level TSV count optimization solution to minimize the TSV count without compromising the chip performance. The experimental results shows we are able to minimize 40% of TSV count in 3D Tree-based FPGA.