Finding best voltage and frequency to shorten power-constrained test time

In a digital test, supply voltage (V_DD), clock frequency (f_test), peak power (P_MAX) and test time (TT) are related parameters. For a given limit P_MAX = P_{MAX func}, normally set by functional specification, we find the optimum V_DD = V_DDopt and f_test = f_opt to minimize TT. A solution is derived analytically from the technology-dependent characterization of semiconductor devices. It is shown that at V_DDopt the peak power any test cycle consumes just equals P_{MAX func} and f_test is fastest that the critical path at V_DDopt will allow. The paper demonstrates how test parameters can be obtained numerically from MATLAB, or experimentally by bench test equipment like National Instruments´ ELVIS. This optimization can cut the test time of ISCAS´89 benchmarks in 180nm CMOS into half.