Innovative practices session 3C: Harnessing the challenges of testability and debug of high speed I/Os

With increasing advances in VLSI technology, process, packaging and architecture, SoC systems continue to increase in complexity. This has resulted in an unprecedented increase in design errors, manufacturing flaws and customer returns in modern VLSI systems related to High Speed IO (HSIO) circuits. The situation will be exacerbated in future systems with increasingly smaller form factors, higher integration complexity, and more complex manufacturing process. This session comprises of three presentations each highlighting the challenges and describing a few solutions for test and debug of HSIOs.