• DocumentCode
    613012
  • Title

    RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning

  • Author

    Muldrey, Barry ; Deyati, Sabyasachi ; Giardino, M. ; Chatterjee, Avhishek

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    2013
  • fDate
    April 29 2013-May 2 2013
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    With trends in mixed-signal systems-on-chip indicating increasingly extreme scaling of device dimensions and higher levels of integration, the tasks of both design and device validation is becoming increasingly complex. Post-silicon validation of mixed-signal/RF systems provides assurances of functionality of complex systems that cannot be asserted by even some of the most advanced simulators. We introduce RAVAGE (from “random;” “validation;” and “generation”), an algorithm for generating stimuli for post-silicon validation of mixed-signal systems. The approach of RAVAGE is new in that no assumption is made about any design anomaly present in the DDT; but rather, the stimulus is generated using the DUT itself with the objective of maximizing the effects of any behavioral differences between the DUT (hardware) and its behavioral model (software) as can be seen in the differences of their response to the same stimulus. Stochastic test generation is used since the exact nature of any behavioral anomaly in the DUT cannot be known a priori. Once a difference is observed, the model parameters are tuned using nonlinear optimization algorithms to remove the difference between its and the DUT´s responses and the process (test generation→tuning) is repeated. If a residual error remains at the end of this process that is larger than a predetermined threshold, then it is concluded that the DUT contains unknown and possibly malicious behaviors that need further investigation. Experimental results on an RF system (hardware) are presented to prove feasibility of the proposed technique.
  • Keywords
    circuit tuning; elemental semiconductors; mixed analogue-digital integrated circuits; optimisation; silicon; system-on-chip; RAVAGE; Si; behavioral model; genetic stimulus evolution; malicious behaviors; mixed signal systems; mixed-signal systems-on-chip; mixed-signal-RF systems; model tuning; nonlinear optimization; post-silicon validation; residual error; stochastic test generation; Genetic algorithms; Integrated circuit modeling; Mathematical model; Radio frequency; Sociology; Statistics; Tuning; automatic test pattern generation; hardware trojan detection; integrated circuit testing; post-silicon validation; radiofrequency integrated circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium (VTS), 2013 IEEE 31st
  • Conference_Location
    Berkeley, CA
  • ISSN
    1093-0167
  • Print_ISBN
    978-1-4673-5542-1
  • Type

    conf

  • DOI
    10.1109/VTS.2013.6548917
  • Filename
    6548917