Relocation of reconfigurable modules on Xilinx FPGA

This paper presents a design flow that allows relocation of reconfigurable modules on Xilinx FPGAs using dynamic partial reconfiguration (DPR). Relocation of these modules is performed without requirements of re-implementing the design. The article describes the relocation procedure based on modifications of major address of the partial configuration bitstream. This approach allows using single partial bitstream for multiple areas in FPGA device. It reduces a number of partial bitstreams stored in memory, saves the implementation time and it can increase dependability of the system. The proposed flow is demonstrated on a simple example with multiplier and adder locations mutually exchanged.