• DocumentCode
    613573
  • Title

    Reliability-aware cross-layer custom instruction screening

  • Author

    Farahani, B.J. ; Azarpeyvand, A. ; Safari, Saeed ; Fakhraie, S. Mehdi

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran
  • fYear
    2013
  • fDate
    8-10 April 2013
  • Firstpage
    258
  • Lastpage
    262
  • Abstract
    Bias Temperature Instability (BTI) and process variation introduce remarkable unpredictability to Custom Instructions (CIs) manufactured at nano-scale technology. Moreover, shrinking the feature size to nanometer levels makes soft error another critical issue of CIs. To tackle these factors, we propose a reliability-aware cross-layer CI screening method. By adding an intermediate phase between the CI generation and CI selection phases, this method enables designers to prune the outputs of the generation phase in order to guarantee that synthesized CIs meet the required reliability constraints. For this purpose, a holistic framework is developed to analyze the combined effects of the BTI and process variation as well as the soft error on the CIs by making a link between circuit-level and system-level information. Based on this information collected from different layers of abstraction, the screening method prunes those CIs which cannot meet the reliability constraints. Experiments illustrate that BTI-unaware CI selection techniques may not meet the desired lifetime because of BTI-induced delay shift of CIs. Moreover, according to the results, a remarkable percentage of CIs is vulnerable to soft error and should not be fed into CI selection phase.
  • Keywords
    nanoelectronics; negative bias temperature instability; radiation hardening (electronics); BTI; bias temperature instability; circuit-level information; custom instruction screening; holistic framework; nanoscale technology; process variation; reliability constraints; reliability-aware cross-layer CI screening; soft error; system-level information; Aging; Delays; Integrated circuit reliability; Logic gates; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013 IEEE 16th International Symposium on
  • Conference_Location
    Karlovy Vary
  • Print_ISBN
    978-1-4673-6135-4
  • Electronic_ISBN
    978-1-4673-6134-7
  • Type

    conf

  • DOI
    10.1109/DDECS.2013.6549829
  • Filename
    6549829